A Flexible Rate Multiplier Circuit with Uniform Pulse Distribution Outputs

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Abstract
In digital integrated circuits (IC's) a synchronous binary-rate multiplier is commercially available, generating a programmable number of output pulses during each internal counting cycle having a length equal to a power of two. These output pulses are not equally divided over that fixed internal counting cycle and the generated binary rate has a fixed denominator. In this note a new type of binary-rate multiplier is described. This circuit allows the programming of both numerator a and denominator b of the rate of the numbers of output and input pulses. It operates in such a way that during a cycle of b pulses the circuit output generates a number of pulses divided over the cycle of b pulses as equally divided as is possible in digital systems.

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