Sparc T4: A Dynamically Threaded Server-on-a-Chip

17 January 2012

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro

Vol. 32 (2) , 8-19
https://doi.org/10.1109/mm.2012.1

Abstract

The Sparc T4 is the next generation of Oracle's multicore, multithreaded 64-bit Sparc server processor. It delivers significant performance improvements over its predecessor, the Sparc T3 processor. The authors describe Sparc T4's key features and detail the microarchitecture of the dynamically threaded S3 processor core, which is implemented on Sparc T4.

Keywords

MULTIPROCESSING SYSTEMS
COMPUTER ARCHITECTURE
MICROPROCESSOR CHIPS

This publication has 2 references indexed in Scilit:

Niagara: A 32-Way Multithreaded Sparc Processor
IEEE Micro, 2005
Neural methods for dynamic branch prediction
ACM Transactions on Computer Systems, 2002