Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide

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Abstract
We studied the diffusion of impurities in dual polysilicon gates, and found that this phenomenon can effectively be treated as diffusion from a constant concentration diffusion source for both p+ and n+ polysilicon gates. We derived a model for the critical time required to obtain a flat profile. We then clarified the thermal budget required for suppressing gate depletion and impurity penetration through a gate oxide. According to our study, the thermal budget for n-type metal-oxide-semiconductor-field-effect-transistor (MOSFET) is always wider than that for p-type MOSFET, and the budget for p-type MOSFET is wide enough for realizing a flat profile without impurity penetration using pure SiO2 if B is available instead of BF2.

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