A high-performance CMOS/SOS device with a gradually doped source—Drain extension structure

1 October 1983

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 4 (10) , 372-374
https://doi.org/10.1109/edl.1983.25768

Abstract

A gradually doped source-drain extension (GDDE) CMOS/SOS structure with n+ poly gate has been used to fabricate a high-performance CMOS/SOS inverter ring oscillator and 1%8 static binary counter. The 0.8-µm gate ring oscillator shows 80-ps stage delay atV_{DD} = 5V, and it achieves 0.1 pJ of speed-power product with 95-ps stage delay. The plasma-etched epi island minimizes the edge leakage current, as shown in subthreshold characteristics.

Keywords

ETCHING
PLASMA APPLICATIONS
LEAKAGE CURRENT
PLASMA TEMPERATURE
PLASMA PROPERTIES
PLASMA DEVICES
IMPLANTS
PLASMA SOURCES
RING OSCILLATORS
FABRICATION

This publication has 0 references indexed in Scilit: