Photoresist-enhanced wafer charging during high current ion implantation
- 24 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Various experiments are described involving the influence of patterned photoresist (PR) on wafer charging during high current arsenic implantation. Use of Stanford 100-mm CHARM-2 test chips allows measurement of both potentials and currents delivered to a wafer during implantation-thus allowing extraction of the J-V characteristic of the beam itself. The results indicate that the placement of the PR is of crucial importance: photoresist on field oxide has a moderate influence on charging, whereas PR on a charge-collection-electrode increases positive charging dramatically. Other PR charging effects discussed include: outgassing, resist thickness, wafer blocked-area (area unable to conduct current to the substrate), wafer surface secondary electron coefficient, and PR surface currents. Also, a model of the ion beam-treated as a plasma-is given to aid in the understanding of PR-enhanced charging.Keywords
This publication has 2 references indexed in Scilit:
- CHARM2: towards an industry-standard wafer surface-charge monitorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Characterization of wafer charging mechanisms and oxide survival prediction methodologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1994