A 7 MB/sec (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 10.4.1-10.4.4
- https://doi.org/10.1109/cicc.1993.590689
Abstract
A mixed-signal, 6.0-MByte/s PRML (partial-response maximum-likelihood) read/write channel has been developed using analog circuits and 20K CMOS gates on a single chip. The 7.5-mm/sup 2/ chip uses a 5-V, 1-/spl mu/m, BiCMOS process with a 6-GHz NPN and a 1-GHz PNP and is packaged in a 100 lead metal QFPK. The overall chip architecture is discussed along with specific analog functions and their circuit techniques. This IC will allow production of a 2-GByte, 3.5-in, rigid disk drive with low error rates.Keywords
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