Layout compaction with minimized delay bound on timing critical paths
- 24 August 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- An efficient algorithm for layout compaction problem with symmetry constraintsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A hierarchy preserving hierarchical compactorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A performance-aimed cell compactor with automatic jogsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Provably good performance-driven global routingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Performance-driven constructive placementPublished by Association for Computing Machinery (ACM) ,1990
- Minplex---a compactor that minimizes the bounding rectangle and individual rectangles in a layoutPublished by Association for Computing Machinery (ACM) ,1986
- An Algorithm to Compact a VLSI Symbolic Layout with Mixed ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983