Polycyclic vector scheduling vs. chaining on 1-port vector supercomputers
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 7 references indexed in Scilit:
- Squeezing more CPU performance out of a Cray-2 by vector block schedulingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Cydra 5 directed dataflow architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- A close look at vector performance of register-to-register vector computers and a new modelPublished by Association for Computing Machinery (ACM) ,1987
- Instruction Issue Logic in Pipelined SupercomputersIEEE Transactions on Computers, 1984
- Efficient code generation for horizontal architecturesACM SIGARCH Computer Architecture News, 1982
- The CRAY-1 computer systemCommunications of the ACM, 1978
- Improving the throughput of a pipeline by insertion of delaysPublished by Association for Computing Machinery (ACM) ,1976