A 32b microprocessor for Smalltalk

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 32-33
https://doi.org/10.1109/isscc.1986.1156983

Abstract

A 32b microprocessor built specially to execute smalltalk will be presented. A 4μm NMOS implementation operates at 400ns per instruction and consists of 36K transistors in a die size of 320×432 mils.

Keywords

MICROPROCESSORS
REGISTERS
DECODING
PROGRAMMABLE LOGIC ARRAYS
COSTS
REDUCED INSTRUCTION SET COMPUTING
MOS DEVICES
MARINE TECHNOLOGY
PIPELINE PROCESSING
ASSEMBLY

This publication has 1 reference indexed in Scilit:

Architecture of SOAR
Published by Association for Computing Machinery (ACM) ,1984