Modeling of hot electron effects on the device parameters for circuit simulation

1 January 1986

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/iedm.1986.191299

Abstract

A practical and realistic assessment of hot electron degradation effects on circuit performances was examined. Device parameters were monitored after each stress operation for NMOS FET's with several different channel lengths. Quantitative descriptions of all the critical parameters as a function of stress time and stress substrate current were established. Device simulations for the transistors with negative fixed interface charges localized near the drain have confirmed the hot-carrier degradation results observed experimentally. Circuit simulation results for a ring oscillator and an inverter chain circuits using the parameters corresponding to the conventional criteria for determining device lifetime and that of a more realistic approach were compared.

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