A video digital signal processor with a vector-pipeline architecture
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A description is given of a 2-GOPS, 60-MIPS video digital signal processor ULSI with a vector-pipeline architecture for video CODEC systems, called the vector digital signal processor (VDSP). The VDSP uses 0.8- mu m CMOS technology and contains a discrete cosine transform (DCT) core as a special processing unit. The vector-pipeline (VP) architecture allows input vector data to be processed in various pipeline configurations. The VDSP performs motion vector detection, motion compensation, DCT/IDCT, loop filtering, quantization/inverse quantization, and variable length coding/decoding specified in CCIT H.261. The encoder and the decoder specified in the subset including the applications of CCIT H.261 (full-CIF mode at 15 frame/s or more, 64 kb/s) can be realized with only two VDSP chips, and only one VDSP chip, respectively, and thus have twice the performance of prior digital signal processors.Keywords
This publication has 1 reference indexed in Scilit:
- A new hardware realization of digital filtersIEEE Transactions on Acoustics, Speech, and Signal Processing, 1974