Array architecture for ATG with 100% fault coverage
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Discusses an array architecture, circuitry and methodology for the automatic generation of test vectors. The architecture has been implemented in a mask programmed version of an antifuse based FPGA. The architecture provides 100% controllability and observability of each node in the circuit. This allows the automatic generation of test vectors with 100% fault coverage independent of the design implemented in the array circuit. In addition to architecture and circuit implementation details, the paper discusses the ATG generation methodology and algorithms, circuit overhead for the test features as well as test times and results Author(s) El-Ayat, K. Actel Corp., Sunnyvale, CA, USA Cahn, R. ; Chung Lau Chan ; Speers, T.Keywords
This publication has 3 references indexed in Scilit:
- On the testing of multiplexersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A CMOS electrically configurable gate arrayIEEE Journal of Solid-State Circuits, 1989
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966