On the proportioning of chip area for multistage Darlington power transistors
- 1 August 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 23 (8) , 870-878
- https://doi.org/10.1109/t-ed.1976.18501
Abstract
A Model has been proposed and solved in which all Darlington circuits may be represented to a first order approximation by five constants, one of which may be normalized. Experimental verification has been provided offering excellent agreement with theory. Several orders of magnitude improvement in current-handling ability have been shown to exist for multistage Darlington circuits over conventional discrete transistors. The allocation of chip area for each stage is extensively discussed as a design aid.Keywords
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