Analog testability analysis and fault diagnosis using behavioral modeling

17 December 2002

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 413-416
https://doi.org/10.1109/cicc.1994.379691

Abstract

This paper presents an efficient strategy for testability analysis and fault diagnosis of analog circuits using behavioral models. A key contribution is a new algorithm for determining analog testa- bility. Experimentally, we determined the testability and faults of a fabricated 10 bit digital-to-analog converter modeled using the analog hardware description language, Cadence-AHDL. Also, we applied the testability analysis at the circuit level usi ng SPICE sensitivity analysis.

Keywords

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