A 33 GB/s 13.4 Mb integrated graphics accelerator and frame buffer

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Abstract
Reported integrated DRAM and logic devices separate DRAM and ASIC logic portions with a traditional memory interface. Although this approach has a number of benefits over the discrete solution, much greater improvements are available by more tightly integrating the DRAM and logic, something not possible at the board level. This device integrates parts of the graphics processor within the DRAM to increase performance. The architecture of one bank of the frame buffer is shown where the pixel processing unit (PPU) and the serial output registers (SORs) are integrated into the DRAM architecture. This allows the bus width between the DRBM frame buffer and the processor to be 4096b.

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