An analog BiCMOS integrated circuit for front-end RDS decoder
- 1 January 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Consumer Electronics
- Vol. 37 (3) , 585-591
- https://doi.org/10.1109/30.85571
Abstract
An analog integrated front-end circuit for the RDS (Radio-Data-System) digital decoder is described. The core of the circuit is an 8th-order switched-capacitor (SC) bandpass filter at 57 kHz with linear-phase response in a 3 kHz bandwidth. A low-offset comparator provides the squared signal for the digital decoder. Antialiasing and smoothing filters are also included in the chip, as well as the clock generation for the SC section; few external components are required. Integrated in a high-performance BiCMOS technology, the circuit operates from a single 5-V supply and dissipates 45 mW. The die size is 5 mm2Keywords
This publication has 4 references indexed in Scilit:
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- SWITCAP: A switched-capacitor network analysis program part I: Basic featuresIEEE Circuits & Systems Magazine, 1983
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