Multiple-process behavioral synthesis for mixed hardware-software systems

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 10801820,p. 10-15
https://doi.org/10.1109/isss.1995.520606

Abstract

Systems composed of microprocessors interacting with ASICs are necessarily multiple-process systems, since the controller in the microprocessor is separate from any controllers on the ASIC. For this reason, the design of such systems offers an opportunity to exploit not only hardware-software tradeoffs, but concurrency tradeoffs as well. The paper describes an automated iterative improvement technique for performing concurrency optimization and hardware-software tradeoffs simultaneously. Experimental results illustrate that addressing these two issues simultaneously enables us to identify a number of interesting cost/performance points that would not have been found otherwise.

Keywords

This publication has 8 references indexed in Scilit:

Adaptation Of Partitioning And High-level Synthesis In Hardware/software Co-synthesis
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
Fast timing analysis for hardware-software co-synthesis
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
A system-design methodology: executable-specification refinement
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
Interactive system-level partitioning with PARTIF
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
Execution-time profiling for multiple-process behavioral synthesis
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995
Hardware-software cosynthesis for digital systems
IEEE Design & Test of Computers, 1993
A model and methodology for hardware-software codesign
IEEE Design & Test of Computers, 1993