Processing Technologies for GaAs Memory LSIs

1 October 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 121-124
https://doi.org/10.1109/gaas.1984.10401297

Abstract

A 16 Kb GaAs static random access memory (SRAM) has been designed adopting direct coupled FET logic (DCFL) circuitry for the main and has been fabricated using self-aligned MESFETs with Self-Aligned Implantation for Ν ⁺ -layer Technology (SAINT). This SRAM consists of more than 10 ⁵ FETs, the largest integrated scale m GaAs ICs. A minimum address access time of 4.1 ns has been achieved with a total power dissipation of 2.52 W.

Keywords

GALLIUM ARSENIDE
LOGIC GATES
FIELD EFFECT TRANSISTORS
RANDOM ACCESS MEMORY
INTEGRATED CIRCUIT INTERCONNECTIONS
METALS
THRESHOLD VOLTAGE

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