Providing a VHDL-interface for proof systems

2 January 2003

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 698-703
https://doi.org/10.1109/eurdac.1992.246187

Abstract

When integrating formal methods into the design process one cannot avoid VHDL. In this paper a VHDL frontend for the proof system LAMBDA is presented. The idea is to provide support for almost the full VHDL language and to generate executable ML descriptions that closely resemble the original VHDL programmed.

Keywords

PROOF SYSTEMS
INTERFACE FOR PROOF
PROVIDING A VHDL INTERFACE

This publication has 1 reference indexed in Scilit:

A formal model of computer architectures for digital system design environments
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990