A 100ns 150mW 64Kbit ROM
- 1 January 1978
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. XXI, 152-153
- https://doi.org/10.1109/isscc.1978.1155829
Abstract
A sub 100ns 64K ROM using standard N-channel silicon-gate technology will be discussed. The ROM organized as 8K words by 8bits per word operates from a single 5V supply and has a typical access time and power of 80ns and 150mW.Keywords
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