An integrable MOS neuristor line

1 January 1976

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE

Vol. 64 (11) , 1630-1632
https://doi.org/10.1109/PROC.1976.10390

Abstract

An integrable MOS design of a neuristor line simulating the conventional properties is presented, the line requiring as few as two sections to simulate the desired properties. In addition the line is low power while consuming no power during the resting state.

Keywords

VOLTAGE
CAPACITANCE
ETCHING
CIRCUIT SIMULATION
EQUIVALENT CIRCUITS
PULSE CIRCUITS
CIRCUIT TESTING
MOS CAPACITORS
ALUMINUM
SILICON