A heuristic algorithm for ordering the columns in one-dimensional logica arrays
- 1 May 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 8 (5) , 547-562
- https://doi.org/10.1109/43.24883
Abstract
No abstract availableKeywords
This publication has 13 references indexed in Scilit:
- Topological Optimization of Multiple-Level Array LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- A Heuristic Algorithm for Gate Assignment in One-Dimensional Array ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Simulated Annealing: Theory and ApplicationsPublished by Springer Nature ,1987
- Convergence of an annealing algorithmMathematical Programming, 1986
- Gate Matrix LayoutIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- SWAMI: A Flexible Logic Implementation SystemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Optimization by Simulated AnnealingScience, 1983
- A Dense Gate Matrix Layout Method for MOS VLSIIEEE Journal of Solid-State Circuits, 1980
- One-dimensional logic gate assignment and interval graphsIEEE Transactions on Circuits and Systems, 1979
- Large Scale Integration of MOS Complex Logic: A Layout MethodIEEE Journal of Solid-State Circuits, 1967