A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography

2 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 10-11
https://doi.org/10.1109/vlsit.1992.200618

Abstract

A recessed stacked capacitor (RSTC) structure to achieve both fine-pattern delineation and high cell capacitance is presented. Using a RSTC structure, an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology has been fabricated. A 25-fF/cell capacitance was obtained in a 0.72 mu m/sup 2/ cell.<>

Keywords

RANDOM ACCESS MEMORY
LITHOGRAPHY
VERY LARGE SCALE INTEGRATION
CAPACITANCE
SILICON
MOS CAPACITORS
DEGRADATION
SPACE TECHNOLOGY
LABORATORIES
FABRICATION

This publication has 1 reference indexed in Scilit:

Improving resolution in photolithography with a phase-shifting mask
IEEE Transactions on Electron Devices, 1982