CMOS quaternary latch

22 June 1989

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 25 (13) , 856-858
https://doi.org/10.1049/el:19890577

Abstract

A new CMOS current-mode quaternary threshold logic latch circuit is presented. This circuit accepts and requantises quaternary logical currents during a SETUP clock mode and latches the input value during the HOLD clock mode. Using logical current increments of 10μA, the quaternary latch has been simulated to have a worst-case, three logic level transition, total SETUP and HOLD time of about 40 ns, and single level transition total SETUP and HOLD time of about 10 ns.

Keywords

CURRENT MODE CMOS
CMOS QUATERNARY LATCH
SINGLE LEVEL TRANSITION
MULTIPLE VALUED LOGIC
REQUANTISES QUATERNARY LOGICAL CURRENTS
SETUP CLOCK MODE
VLSI COMPATIBLE
THREE LOGIC LEVEL TRANSITION
LOGICAL CURRENT INCREMENTS
10 NS
HOLD CLOCK MODE
HOLD TIME
CURRENT-MODE QUATERNARY THRESHOLD LOGIC LATCH
40 NS

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