Directions in CMOS technology

1 January 1983

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 151-154
https://doi.org/10.1109/iedm.1983.190464

Abstract

This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region. In that context, the authors review bulk CMOS technology from 2µm to sub-micron features based upon existing device characteristics, and also discuss directions for further downward scaling.

Keywords

CMOS TECHNOLOGY
CMOS PROCESS
VERY LARGE SCALE INTEGRATION
MOS DEVICES
IMPURITIES
LARGE SCALE INTEGRATION
CMOS LOGIC CIRCUITS
LABORATORIES
TECHNOLOGICAL INNOVATION
BATTERIES

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