Design, performance, and extensions of the RAM-DFE architecture
- 1 March 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Magnetics
- Vol. 31 (2) , 1196-1201
- https://doi.org/10.1109/20.364806
Abstract
The design and performance of an adaptive RAM-Decision feedback equalizer integrated circuit (RAM-DFE IC) for magnetic recording channels is presented. The 0.8 /spl mu/m BICMOS digital chip has been integrated with discrete analog components in a 54 Mbps read channel. Description of the IC implementation details techniques to reduce latency and outlines tradeoffs between performance and complexity. In an effort to achieve higher throughput, alternative decision feedback loop architectures based on look-ahead computation are evaluated. A hybrid RAM/linear architecture is found to approach 150 Mbps throughput with implementational advantages over both RAM and linear feedback filters.Keywords
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