Impurity contamination of the SiO2 layer on Si wafers during ion etching

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Abstract
Impurity contamination of the surface layer takes place during 1 keV argon ion bombardment even when etching is only several hundred Å deep. The causes of contamination of the SiO2 layer on Si wafers are investigated using a conventional etching system. The contamination is found to be due to redeposition of sputtered materials on the wafer, impurity ion drift through the SiO2 layer caused by the electric field, and thermal diffusion. It is necessary to avoid using materials containing impurity atoms near the ion-bombarded area, to neutralize surface charges during etching, and to keep the substrate temperature close to room temperature. Under the above conditions, we obtained etched SiO2 layers with mobile ion concentrations less than 1011 e/cm−2 after annealing and BT(bias temperature) treatments.

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