A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS
- 1 February 2008
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 184-605
- https://doi.org/10.1109/isscc.2008.4523118
Abstract
In this paper, a CMOS implementation of phased-array receiver front-end, based on a widely tunable QVCO is presented. Each path achieves 30dB of gain and a minimum NF of 7.1dB, yielding a system NF of 4.1dB. The overall current draw is 54mA from a 1.2V supply. Additionally, a calibration procedure to mitigate the analog impairments imposed by the proposed implementation is demonstrated.Keywords
This publication has 4 references indexed in Scilit:
- A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and DividerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2007
- A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Transmitter and Local LO-Path Phase ShiftingIEEE Journal of Solid-State Circuits, 2006
- A 60-GHz CMOS Receiver Front-EndIEEE Journal of Solid-State Circuits, 2005
- 38-43 GHz quadrature VCO on 90 nm VLSI CMOS with feedback frequency tuningPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005