A high density CMOS inverter with stacked transistors

1 October 1981

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 2 (10) , 250-251
https://doi.org/10.1109/EDL.1981.25421

Abstract

This paper describes a complete CMOS inverter, whose P-channel transistor is made from laser annealed polycrystalline silicon and is superimposed upon the N-channel transistor. The single gate is common to both transistors. The process is NMOS compatible and polysilicon transistors with channel lengths down to 4 micrometers have been made.

Keywords

INVERTERS
SILICON
ANNEALING
THRESHOLD VOLTAGE
MOS DEVICES
CMOS TECHNOLOGY
DOPING
CMOS PROCESS
POWER LASERS
SEMICONDUCTOR LASERS

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