Conventional poly-Si gate MOS-transistors with a novel, ultra-thin Hf-oxide layer

1 March 2004

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 167-168
https://doi.org/10.1109/vlsit.2003.1221138

Abstract

Conventional poly-Si gate MOS transistors with a high-k gate-dielectric were fabricated using a novel, ultra-thin Hf-oxide. Various integration effects on the high-k layer were studied such as Si-surface preparation, deposition conditions, and post-deposition anneals, demonstrating EOT of 1.6 to 1.2 nm and excellent gate leakage current. Promising transistor behaviors were obtained including electron mobility up to 90% of SiO/sub 2/ at both peak and high-field.

Keywords

HIGH-K GATE DIELECTRICS
HIGH K DIELECTRIC MATERIALS
SURFACE TREATMENT
MOSFETS
ANNEALING
LEAKAGE CURRENT
ELECTRON MOBILITY
GATE LEAKAGE
TEMPERATURE
MOS DEVICES

This publication has 1 reference indexed in Scilit:

Cost-effective cleaning and high-quality thin gate oxides
IBM Journal of Research and Development, 1999