An algorithm for performance-driven initial placement of small-cell ICs

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Abstract
In this paper an algorithm k described for obtaining an initial placement of small-cell ICS subject to performance constraints. The algorithm employs an effective nonlinear wirelength function and an accurate timing model using a block-oriented representation of paths. By introducing the concept of a reduced forest of timing constraints for capturing the structure inherent in the constraints an efficient algorithm for performance driven initial placement is developed and its finiteness proved under less stringent conditions than [JSK90]. In addition, it does not require an initial feasible solution. The algorithm presented in [JSK90] required an initial feasible solution, which is computationslly expensive, taking over 9 hours for an example with 1418 modules. The new algorithm presented in this paper is shown to be effective on practical examples. For the example with 1418 modules, it is able to find an optimal solution in under 8 minutes of CPU time without requiring a feasible solution. Limited space necessitated a highly simplified presentation of the algorithm here. Details may be found in [Sri90].

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