ISDN U transceiver algorithm, development system, and performance
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Motorola and BNR are currently developing the MC145472, a single-chip implementation of a 2B1Q ANSI standard U-interface transceiver for ISDN (integrated services digital network) basic rate access (BRA). The transceiver provides full duplex transmission of 160 kb/s over two-wire nonloaded outside plant loops and is designed to meet the ANSI T1.601 1988 standards for use in both LT and NT1 applications. Its implementation involves state-of-the-art analog and digital signal processing (DSP) technology. The authors describe the functions and verifications of the transceiver, with emphasis on the DSP technology used for echo cancellation, equalization, and timing recovery; the design methodology and hardware testbed used to develop the transceiver algorithms; and performance results for the transceiver under both laboratory and field conditions.Keywords
This publication has 4 references indexed in Scilit:
- Architecture of the 2B1Q symbol receiver in the MC145472 ISDN U transceiverPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Nonlinear echo cancellers based on transpose distributed arithmeticIEEE Transactions on Circuits and Systems, 1988
- An economical class of digital filters for decimation and interpolationIEEE Transactions on Acoustics, Speech, and Signal Processing, 1981
- Timing Recovery in Digital Synchronous Data ReceiversIEEE Transactions on Communications, 1976