A methodology for the verification of a "system on chip"
- 20 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 574-579
- https://doi.org/10.1109/dac.1999.781380
Abstract
No abstract availableKeywords
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- Test program generation for functional verification of PowerPC processors in IBMPublished by Association for Computing Machinery (ACM) ,1995
- Verification of the IBM RISC System/6000 by a dynamic biased pseudo-random test program generatorIBM Systems Journal, 1991