Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2 nm

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Abstract
The high performance 0.25 /spl mu/m dual gate CMOS with ultrathin gate oxide of 2 nm is demonstrated for low-voltage logic application. The boron penetration can effectively be suppressed by the nitrogen implantation technique, even if the gate oxide film is reduced to 2 nm. Moreover the inverter delay with an Al interconnect load can be remarkably improved by the highly drivable MOSFETs with thin gate oxide for low-voltage operation. Furthermore, the hot carrier degradation of NMOSFETs can be suppressed as reducing the oxide thickness. However it is found that the hot-carrier degradation of PMOSFETs is enhanced in thin-oxide region under channel hot-hole injection.

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