Fault simulation and test pattern generation at the multiple-valued switch level
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The aim of this paper is to specify a fault simulation and test pattern generation environment, which includes a multiple-valued algebra, allows the natural treatment of loops and bidirectional devices, and models the physical failures. The main idea of this work is to define what is possible when no extraction to gate level and no creation of transistor groups are performed.Keywords
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