Low-power dividerless frequency synthesis using aperture phase detection
- 1 January 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 33 (12) , 2232-2239
- https://doi.org/10.1109/4.735707
Abstract
A phase-locked-loop (PLL)-based frequency synthe- sizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a result of the power saved by eliminating the divider. The PLL's loop bandwidth is measured to be 6 MHz, with a reference spurious level of 47 dBc. The front-end receiver, including the synthesizer, is fabricated in a 0.5- m, triple-metal, single-poly CMOS process and operates on a 2.5-V supply.Keywords
This publication has 2 references indexed in Scilit:
- A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filtersIEEE Journal of Solid-State Circuits, 1998
- A 1.6-GHz CMOS PLL with on-chip loop filterIEEE Journal of Solid-State Circuits, 1998