Rambist builder: a methodology for automatic built-in self-test design of embedded rams

25 August 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 50-56
https://doi.org/10.1109/mtdt.1996.782492

Abstract

In this paper, we report a built-in self-test methodology for embedded RAMs. A CAD tool has been developed to synthesize the BIST circuitry for the compiled RAMs. The blocks such as address generator, pattern generator, multiplexers, state machine, control logic and comparator are automatically synthesized with this tool. The BIST logic is personalized to the RAM configuration and its physical bit map. This provides coverage of all stuck-at, state transition and coupling faults. In multi-port RAMs port-coupling faults are also detected. RAM addresses are generated by the address generator based upon the March algorithm. A set of multiplexers selects the path to the address, data and control lines, either from the RAM (during normal operation), or from the pattern generator (during test mode). The state machine and control logic provide signals for read, write, port selection and start/end. A comparator evaluates the data written during the write cycle against the RAM's output data to generate a pass/fail flag.

Keywords

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