A fast 8K × 8 mixed CMOS static RAM

1 September 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 32 (9) , 1792-1796
https://doi.org/10.1109/T-ED.1985.22199

Abstract

This paper describes a fast 8K × 8 static RAM fabricated with a mixed CMOS technology. To realize a fast access time and yet a low active power, a block-oriented die architecture with four submodules and a new sense amplifier are applied. An address access time of 34 ns and a chip select access time of 38 ns have been achieved at an active power of 90 mW. In addition to redundant memory cells, the RAM incorporates a spare element disable (SED) function to make it easy to obtain the information of the replaced memory cell. Another feature is a high latchup immunity of the CMOS peripheral circuits. This is obtained from an optimized well structure and guard bands around the wells. A 2-µm design rule combined with the double-level polysilicon layer allowed for layout of the NMOS memory cell in 266.5 µm2and design of the die in 34.3 mm2.

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