CMOS PA-RISC processor for a new family of workstations
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A novel low-cost, high-performance RISC (reduced instruction set computer) processor chip set implementing Hewlett Packard's PA-RISC instruction set has been developed. The design consists of a CPU chip containing 577 K transistors implemented in HP's CMOS26 technology and a floating-point coprocessor containing 640 K transistors and implemented in Texas Instruments' EPIC-2 CMOS technology. Key features of the design include a 66 MHz clock frequency, large configurable cache memories utilizing industry standard SRAMs, and several implementation features designed to improve floating-point and graphics performance.<>Keywords
This publication has 8 references indexed in Scilit:
- A 30 MIPS VLSI CPUPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Electrical design methodology of a 407 pin multi-layer ceramic packagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Architecture and compiler enhancements for PA-RISC workstationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- System design for a low cost PA-RISC desktop workstationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 65MHz Floating-point Coprocessor For A RISC ProcessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- A CMOS RISC CPU designed for sustained high performance on large applicationsIEEE Journal of Solid-State Circuits, 1990
- Precision architectureComputer, 1989
- A 32-bit VLSI CPU with 15-MIPS peak performanceIEEE Journal of Solid-State Circuits, 1987