Etched profile distortions in high density electron cyclotron resonance plasma

Abstract
Recent studies of electron cyclotron resonance plasma etching for fabricating the gate electrode of metal‐oxide‐semiconductor large‐scale integrated circuits indicate a serious problem in the etched profiles. The problem is a local pattern distortion caused by a charge buildup of the patterns. We report basic investigations of the etched profiles and propose the model for local side etch. Plasma parameters are measured by the electrostatic probes. The relationships between the local pattern distortion and the plasma properties are investigated. Lowering the electron temperature perpendicular to the surface normal is one of the most effective techniques for eliminating the local side etch. Lowering the electron temperature is enhanced by setting the wafer at the lower magnetic field. As the large space charge bends the ion trajectories, the lower ion current density is also effective to reduce the local side etch. The smoothly decreasing distribution of plasma potential which accelerates the ions can reduce the local side etch in spite of the higher current density.

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