A 4096-bit high-speed emitter-coupled-logic (ECL) compatible random-access memory
- 1 October 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 10 (5) , 262-267
- https://doi.org/10.1109/jssc.1975.1050609
Abstract
A 4096-bit pseudostatic MOS random-access memory with emitter-coupled (ECL) compatibility on all inputs including clocks is described. This device exhibits access times of under 80 ns and cycle times of under 150 ns with a standby dissipation of 300 mW. The fully decoded memory is fabricated on a 204/spl times/237 mil silicon chip and is assembled in a 22-lead ceramic dual-in-line package.Keywords
This publication has 1 reference indexed in Scilit:
- Charge pumping in MOS devicesIEEE Transactions on Electron Devices, 1969