Dynamic decentralized cache schemes for mimd parallel processors
- 1 January 1984
- journal article
- Published by Association for Computing Machinery (ACM) in ACM SIGARCH Computer Architecture News
- Vol. 12 (3) , 340-347
- https://doi.org/10.1145/773453.808203
Abstract
This paper presents two cache schemes for a shared-memory shared bus multiprocessor. Both schemes feature decentralized consistency control and dynamic type classification of the datum cached (i.e. read-only, local, or shared). It is shown how to exploit these features to minimize the shared bus traffic. The broadcasting ability of the shared bus is used not only to signal an event but also to distribute data. In addition, by introducing a new synchronization construct, i.e. the Test-and-Test-and-Set instruction, many of the traditional. parallell processing “hot spots” or bottlenecks are eliminated. Sketches of formal correctness proofs for the proposed schemes are also presented. It appears that moderately large parallel processors can be designed by employing the principles presented in this paper.Keywords
This publication has 2 references indexed in Scilit:
- Using cache memory to reduce processor-memory trafficPublished by Association for Computing Machinery (ACM) ,1983
- Cache system design in the tightly coupled multiprocessor systemPublished by Association for Computing Machinery (ACM) ,1976