A new CR-delay circuit technology for high-density and high-speed DRAMs

Publisher Website

1 January 1988

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 75-76
https://doi.org/10.1109/vlsic.1988.1037430

Abstract

No abstract available

This publication has 1 reference indexed in Scilit:

A 60-ns 4-Mbit CMOS DRAM with built-in selftest function
IEEE Journal of Solid-State Circuits, 1987