BANGALORE: an algorithm for the optimal minimization of programmable logic arrays

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Abstract
The paper describes BANGALORE, a minterm based algorithm for the optimal minimization of programmable logic arrays (PLA), The algorithm is a divide and conquer algorithm and is carried out by five procedures. The algorithm is mainly guided by two parameters, the degree of adjacency (DA) and the candidate product term (CPT), which are selectively computed for those minterms that participate in the generation of product terms constituting the optimal solution. The algorithm also handles a multiple output function whose individual functions are cyclic functions. For the implementation of the multiple output function using a PLA, the algorithm produces the C-matrix (AND plane) and the D-matrix (OR plane), where the number of product lines and the cross points are minimal. The algorithm does not generate any superfluous product term or the OFF set of any function. Consequently, the number of computations turn out to be quite minimal. As such, it is likely to be more efficient and faster than many existing logic minimization algorithms.

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