Full copper wiring in a sub-0.25 μm CMOS ULSI technology

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Abstract
We present the first fully integrated ULSI CMOS/copper interconnect technology. Up to 6 Cu wiring levels are built at minimum metal-contacted pitch of 0.63 /spl mu/m, with W local-interconnect and contact levels and a polycontacted pitch of 0.81 /spl mu/m, on a fully-scaled sub 0.25 /spl mu/m, 1.8 V CMOS technology. The Cu wiring has advantages of significantly lower resistance, higher allowed current density, and increased scalability, relative to comparable Ti/Al(Cu) wiring. These benefits in turn have enabled the scaling of pitch and thickness, from reduced-capacitance, high-density lower levels to low RC global wiring levels, consistent with high-performance and high-density needs. The integrated Cu hardware was evaluated according to a comprehensive set of yield, reliability, and stress tests. This included fully functional, high-density 288 K SRAM chips which were packaged into product modules and successfully tested for reliability. Overall, we find the results for full Cu wiring meet or exceed the standards set by our Al(Cu)/W-stud technology.

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