DEEP LEVEL DEFECTS IN SILICON AFTER BEAM PROCESSING IN THE SOLID PHASE REGIME

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Abstract
Recent investigations of defects in cw beam processed silicon are reviewed, with emphasis on electrical characterization. Defect levels have been observed in concentrations of 1014 - 1015 cm-3 in surface layers of silicon wafers, either ion-implanted or virgin, following beam processing in the solid phase regime. Deep Level Transient Spectroscopy (DLTS) has provided a unique insight into the microscopic nature of these defects, and the mechanisms of defect production. Practical informations concerning the conditions for defect introduction and removal have been obtained. Implications regarding device fabrication and thermally induced defects in silicon will be discussed

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