Area-efficient high speed decoding schemes for turbo/MAP decoders
- 13 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 4, 2633-2636
- https://doi.org/10.1109/icassp.2001.940542
Abstract
Turbo decoders inherently have a large latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, two types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes introduce no performance degradation in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presentedKeywords
This publication has 2 references indexed in Scilit:
- Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An intuitive justification and a simplified implementation of the MAP decoder for convolutional codesIEEE Journal on Selected Areas in Communications, 1998