Snubber Circuit for High-Power Gate Turn-Off Thyristors

Abstract
A snubber circuit calculation model for high-power gate turn-off thyristors (GTO's) was proposed to consider problems which must be investigated for snubber circuit design. The calculated GTO waveforms showed good agreement with experimental values obtained by a GTO chopper circuit for both a resistive and inductive load case. Problems to be considered for the snubber design, such as voltage spike reduction, maximum GTO anode current, and switching power, were discussed using the calculation model. Design criteria for the snubber circuit were successfully established, introducing allowable maximum voltage spikes to avoid failures due to current crowding during the GTO interval and excessive voltage applied over maximum blocking voltage rating. Minimum switching power loss dissipated inside the GTO and the snubber resistor was also calculated, taking the design criteria into consideration. As results of the calculations, the snubber circuit stray inductance was found to play an important role in optimizing the minimum switching power loss, especially for large anode current and large stray inductance in a main circuit. 1983.

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