Design and characterization of 3 μm bubble memory chips utilizing Y-Y patterns

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Abstract
Major-minor organized bubble memory chips have been developed utilizing 14 μm period Y-Y propagation circuits. First type is a 75 kbit memory chip consisting of four major-minor units for high performance demands. Designed access time and data rate for 300 kHz drive are 0.3 nsec and 2×600 kbits/sec, respectively. Second type is a single unit major-minor 78 kbit memory chip for medium access time use. Main chip design features are as follows: (1) 14 μm Y shaped Permalloy circuits are used throughout the chip, except for the 18 μm chevron stretcher. (2) Y-Y transfer gates have been tailored in order to adapt to Y patterns. (3) A thin film Permalloy detector is used for the sake of large output (15 mV/2 mA) amd O-π phase detection. The 3 μm bubble chips are fabricated on (YSmTmCa)3(FeGe)5O12 garnet films. Wafers are processed through 3 evaporation steps and 5 masks. Total 20 Oe operating bias margin is obtained at 300 kHz for 50 Oe drive field.

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