Labyrinth: a homogeneous computational medium
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
As a RAM-based reconfigurable logic array, Labyrinth provides the flexibility and malleability of software with the performance of a dedicated circuit. With a single bit register and a half adder per cell, the architecture is optimized for register intensive, massively parallel algorithms. The fine-grained, highly-symmetric architecture scales very naturally and facilitates compact circuit layouts. A 64-cell test chip has been successfully built and tested, and a 4096-cell chip is in the final stages of preparation for fabrication Author(s) Furtek, F. Concurrent Logic Inc., Arlington, MA, USA Stone, G. ; Jones, I.Keywords
This publication has 1 reference indexed in Scilit:
- An Approach to Highly Integrated, Computer-Maintained Cellular ArraysIEEE Transactions on Computers, 1977